1. Field of the Invention
The present invention relates to power-on reset circuits, and more particularly, to a power-on reset circuit and power-on reset method of a semiconductor integrated circuit using a plurality of power sources.
2. Discussion of the Related Art
Semiconductor integrated circuit devices generally include a power-on reset circuit to prevent abnormal operations when a power source is applied thereto. Generally, once the power source is applied to the semiconductor integrated circuit device and reaches a predetermined voltage, the power-on reset circuit provides a reset signal for initializing components of a semiconductor memory device, such as flip-flops, latches, counters, registers, and the like. A typical voltage detection circuit outputs an activated power-on reset signal if the power source voltage reaches a predetermined voltage when the power is on. Internal components of the semiconductor integrated circuit are reset to an initial state in response to the activated power-on reset signal. Then, if the power source voltage reaches a normal operating voltage, the power-on reset signal is deactivated. As demands for high-speed integrated circuits are increasing, integrated circuits utilizing a plurality of power sources are more widely used. For example, separate power sources are used for input/output pins, input/output buffers, memory cells, and the like.
FIG. 1 is a schematic diagram showing a problem caused in a conventional power-on reset circuit of a semiconductor memory device 100 using a plurality of power sources. If a voltage level of a power source VDD1 supplied to a typical memory device reaches a predetermined voltage, a power-on reset circuit 10 detects the voltage level and generates a pulse with a constant width, i.e., a power-on reset signal POR. The power-on reset signal POR sets all the nodes needing to be initialized within the memory device to logic high states. Here, the nodes include a node N1 connected with a first latch 30 and a node N2 connected with a second latch 50.
Unfortunately, although the power source VDD1 reaches the predetermined voltage level to generate the power-on reset signal and then reaches a stable voltage level, a power source VDD2 might not reach a stable voltage level prior to the POR pulse. Therefore, in a PMOS transistor (PM1) 70 having a drain electrode connected to the node N1, a source electrode connected to the power source VDD2 and a gate electrode receiving the power-on reset signal, the source electrode of the PMOS transistor 70 does not reach a stable voltage level and thus the PMOS transistor 70 does not activate. As a result, the initialization of the node N1 fails.
In addition, after the power-on reset signal POR generated in response to the power source VDD1 by the power-on reset circuit 10 is delayed for a predetermined time, a noise may occur in the power source VDD3 that reaches a stable state when the power-on reset signal POR reaches a gate electrode of a PMOS transistor (PM2) 90 connected between a power source VDD3 and the node N2. In other words, in a case where a noise occurs after the power source VDD1 reaches a stable voltage level or in a case where a noise occurs at the power source VDD3 itself, since the power source VDD3 is unstable at a point when the power-on reset signal POR reaches the gate electrode of the PMOS transistor 90, the PMOS transistor 90 is not activated. As a result, the initialization of the node N2 fails.
Accordingly, it is desirable to provide a stable power-on reset circuit and method for a semiconductor memory device using a plurality of power sources.